The present invention relates to an integrated circuit fabrication, and more particularly to a process of fabricating a self-aligned bipolar junction transistor (BJT) with a shallow base junction to achieve higher gain.
BJTs are well known in the integrated-circuit technical field. FIG. 1 shows a schematic cross-section of a conventional BJT. The BJT is fabricated in an N-type silicon substrate 1 which serves as the collector region of the BJT. A P-well 10 is diffused into the silicon substrate 1 to form the base region 10 of the BJT. An N.sup.+ -type diffusion region 12 is formed in the base region 10, and serves as the emitter region of the BJT. A P.sup.+ -type base contact. region 14 is diffused into the base region 10, and an N.sup.+ -type collector contact region 16 is formed in the silicon substrate 1.
In the conventional process of fabricating such BJTs, formation of the N.sup.+ emitter region 12 and of the P.sup.+ base contact region 14 in the P-well 10, i.e. the base region, is done by photolithography and implantation technologies. The P-well 10 has to occupy a surfrelent size to tolerate the mask misalignment problem. This prevents the efficient utilization of limited wafer size. Furthermore, the conventional process can not easily form a shallow junction for the base region 10, and thus it is difficult for the fabricated BJT to achieve higher gain.